I. Field of the Disclosure
The technology of the disclosure relates generally to processing of pipelined computer instructions in central processing unit (CPU)-based systems.
II. Background
The advent of “instruction pipelining” in modern computer architectures has yielded improved utilization of CPU resources and faster execution times of computer applications. Instruction pipelining is a processing technique whereby a throughput of computer instructions being processed by a CPU may be increased by splitting the processing of each instruction into a series of steps. The instructions are then executed in a “processor pipeline” composed of multiple stages, with each stage carrying out one of the steps for each of a series of instructions. As a result, in each CPU clock cycle, steps for multiple instructions may be evaluated in parallel. A CPU may employ multiple processor pipelines to further boost performance.
The performance of a CPU in a pipelined computing architecture may be hampered both by the issuance of unnecessary or redundant instructions, as well as by the occurrence of pipeline “hazards,” which may prevent an issued instruction from executing during its designated CPU clock cycle. For instance, in some instruction set architectures, execution of a conditional write instruction may include reading a value from a target register, evaluating a condition, and writing a value to the target register based on the evaluation of the condition. In such a case, a pipeline hazard (specifically, a “read-after—write” hazard) may be encountered. To resolve the read-after-write hazard, the CPU may “stall” or delay execution of the second conditional write instruction until the first conditional write instruction has completely executed, thus further decreasing the effective throughput of the CPU.